Many implantable medical devices (IMDs) include circuits for delivering electrical stimulation to tissue. For example, implantable pacing, defibrillation, and cardioversion devices are designed to deliver electrical stimulation to the heart via electrodes that are in contact with cardiac tissue. Other types of implantable devices such as neuro-stimulation systems are known for delivering electrical stimulation to muscle, nerve, or other types of tissue within a patient's body.
IMDs that deliver electrical stimulation generally include output switching networks to selectively couple stimulation energy to cardiac, muscular, or neurologic tissue from batteries and/or capacitors under supervisory control of algorithms or firmware resident in the device. In the prior art, these switches are generally implemented in CMOS technology using CMOS Field Effect Transistors (FETs). These transistors can be readily implemented in silicon devices using three to five-micron, or larger, CMOS technology. However, as the feature size of the CMOS FETs is decreased below three microns, the breakdown voltage of the FETs is also decreased. If the breakdown voltage decreases to a voltage that is at, or near, the voltage that will be applied across a FET, stimulation pulse parasitic leakage will occur, causing ineffective stimulation, increasing battery current drain, and potentially resulting in damage to the integrated circuit.
One proposed mechanism for solving the above-described problem involves implementing all switching circuitry in at least a three-micron technology in a first integrated circuit, while implementing all other circuitry for the IMD in another integrated circuit employing smaller-sized gates. This type of approach is described in U.S. Pat. No. 5,833,710 to Jacobson. This proposed solution adds an additional integrated circuit to the design, increasing system size and cost.
Moreover, this method requires the addition of hybrid circuit interconnects to couple the multiple integrated circuits. These interconnections are costly to manufacture and are prone to failure. Also, interconnections on the hybrid circuit level generally consume more current than interconnections contained within a single integrated circuit.
Another solution to the problem involves employing several FET transistors in series in place of a single FET to implement a switching function. This allows a given voltage drop to be shared by multiple transistors such that the likelihood of circuit damage and/or leakage is decreased. However, this solution has the disadvantage of greatly increasing the amount of silicon area required to implement each switch. Additionally, the design is complicated because the multiple FETs implementing a single switch must be enabled in a predetermined order to prevent the full voltage drop from being experienced by a single FET even for a very brief period, since this could damage the circuit or cause large leakage currents. The implementation of this design approach therefore generally results in the use of a significantly increased silicon die area.
Yet another approach is discussed in U.S. Pat. No. 5,097,830 to Eikefjord, et al. This patent describes an external defibrillator that incorporates transfer relays to deliver the defibrillation pulse to a patient. This design consumes a relatively large amount of space.
While the above discussion focuses on switching networks used within output circuitry of an IMD, those skilled in the art will recognize that other switches in an IMD are associated with problems similar to those discussed above. What is needed, therefore, is an improved switching system and method for use in implementing a switching function within an IMD or associated lead that can be robustly implemented using a substantially smaller die area and/or meet the low power requirements needed to conserve battery energy in an implanted device.